This week at the Design, Automation and Test in Europe (DATE) conference, Kevin Murray is presenting some exciting work I’ve done in collaboration with Kevin, his supervisor Vaughn Betz at the University of Toronto, and Andrea Suardi at Imperial College.

I’ve been working for a while on the idea that one form of approximate computing derives from circuit overclocking. The idea is that if you overclock a circuit then this may induce some error. However the error may be small or rare, despite a very significant performance enhancement. We’ve shown, for example, that such tradeoffs make sense for image processing hardware and – excitingly – that the tradeoffs themselves can be improved by adopting “overclocking-friendly” number representations.

In the work I’ve done on this topic to date, the intuition that a given circuit is “overclocking friendly” for a certain set of input data has been a human one. In this latest paper we move to an automated approach.

Once we accept the possibility of overclocking, our circuit timing analysis has to totally change – we can’t any longer be content with bounding the worst-case delay of a circuit, because we’re aiming to violate this worst case by design. What we’re really after is a **histogram** of timing critical paths – allowing us to answer questions like “what’s the chance that we’ll see a critical path longer than this in any given clock period?” Different input values and different switching activities give rise to the sensitization of different paths, leading to different timing on each clock cycle.

This paper’s fundamental contribution is to show that the #SAT probem can be efficiently used to quantify these probabilities, giving rise to the first method for determining at synthesis time the affinity of a given circuit to approximation-by-overclocking.

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Anupam

said:Interesting work George – I will go through the paper. With an earlier PhD student of mine, I have been looking into connecting approximate computing to high-level synthesis flows. Here are two papers that were presented in last years in that context, fully validated with a fabricated chip – done in collaboration with EPFL. Hope that is useful for your work.

http://dl.acm.org/citation.cfm?id=2755839

http://dl.acm.org/citation.cfm?doid=2897937.2898095

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George Constantinides

said:Thanks, Anupam. The first paper in particular looks quite relevant – we’ll read and discuss in my group! You may also be interested in the work we’ve done on dynamically tuning timing on FPGAs which is also up-and-running in the lab, e.g. http://cas.ee.ic.ac.uk/people/gac1/pubs/JoshFPL13.pdf. I hope to catch you in Singapore!

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