My research sits where computation meets physical implementation: digital hardware, arithmetic, machine learning, and the route from code or mathematical intention to efficient systems. I am interested in computation as something with mathematical structure, physical cost, and social meaning, and in how better representations, architectures, abstractions, and proofs can change what is possible.
Research
My work combines elements of computer science, electronic engineering, and mathematics. Current themes include hardware-aware machine learning, hardware-native neural networks, high-level synthesis, arithmetic and precision, equality-saturation and e-graph rewriting, and semantic or intensional views of computation.
For publications, see my DBLP profile. For research notes and commentary, see the Research archive on my blog.
Teaching
I teach final-year and masters projects, and first-year Digital Electronics and Computer Architecture.
I supervise a small number of PhD students each year. For prospective students, see Join Us; for current students and alumni, see People.
Professional Activities (selected)
I have chaired the major FPGA conferences FPGA, FPL and FPT, and have served on many programme committees across reconfigurable computing, EDA, arithmetic, and related areas. I am a steering committee member of FPGA. I have also been a member of a variety of national and international strategic bodies including EPSRC’s ICT Strategic Advisory Team and the League of European Research Universities Doctoral Studies steering group.
External Collaboration
I work with external partners where deep technical judgement is needed about computation in its physical form, including patent litigation, technical review, startup collaboration, and research sponsorship. See Consulting and Industry Collaboration.
George A. Constantinides 